Shakti is the first Microprocessor of India and is one of the biggest achievements of our country. It is an open-source RISC-V processor (instruction set architecture) developed by IIT students Madras, India. It is used for building open source, production-grade processors and associated components like peripheral IPs, verification tools, interconnect fabrics, SOC tools, and storage controllers. The chip can be used in low-power wireless systems and networking systems.
According to the announcement of Professor Veezhinathan (Department of Computer Science and Engineering at IITM), Shakti is designed in a way that it will never get outdated.
The reason being it is built keeping international standards in mind and it is among the few open-source microprocessors available in the world market today.
The root concept in the making of this microprocessor started in 2011. Finally, the project gained the speed in 2017, when the Indian Government granted the fund of INR 11 Crore to it.
To build Shakti, the students took assistance from Intel and its 22nm FinFET Technology using which they were able to aim and build 6 variants of processors based on the RISC-V ISA.
Shakti is also being used to develop a base VLSI flow to contribute to the large part of the ecosystem. All the other parts of Shakti might not be open-source, but the source code, the scripts, and the environment to plug-in SHAKTI components are open-source and patent-free. This means, that the source code can be used, modified, and distributed easily as long as it meets the license policies.
The Software Development Kit (SDK) is available to the public on GitLab.
The microprocessor has now become so successful that the designing, functionalities, and the security measures are being asked by several other countries.
As explained by Shakti Team here are the various ecosystem components that cater to different segments of the market:
- Embedded class processor
- Meant for low-power and low compute applications
- Capable of running basic RTOSs like Zephyr, FreeRTOS, and eChronos.
- Market segments include smart-cards, motor-controls, IoT sensors, and robotic platforms
- A controller class of processors aimed to control mid-range application workloads
- 32-bit 3-8 stage in-order variant aimed at 50-250 Mhz microcontroller variants
- IoT variants will have compressed/reduced ISA support
- Fault-Tolerant variants for ISO26262 applications
- Optional memory protection with low power static design
- Based on performance-oriented features like multi-threading, out-of-order execution, non-blocking caches, aggressive branch prediction, and deep pipeline stages
- Target operating range – 1.5-2.5 GHz
- 64-bit, 1-4 core, 5-8 stage, aimed at 200-1Ghz industrial control / general purpose applications
- Devices aimed at networking applications will have dual-quad issue support
- Other features – shared L2 cache, AXI bus
- Mobile class processor with maximum 8 cores (the cores are a combination of C and I class cores) aimed at general purpose compute, low-end server and mobile applications
- The TileLink topology is customizable and thus it allows optimizations for various power/performance targets
- The core complex of 2 or 4 cores will share an L2 cache while L3 caches are optional and are typically expected to be used in desktop type applications.
- Frequency up to 2.5 GHz, optional NoC fabric
- 64-bit superscalar, multi-threaded variant for desktop/server applications
- An enhanced version of the I-class, with quad-issue and multi-threading support
- Cores are expected to use dedicated L2 caches and segmented L3 caches
- 1.2-3Ghz, 2-16 cores, crossbar/ring interconnect, segmented L3 cache
- 256/512 bit SIMD
- Hybrid Memory Cube support
- RapidIO based external cache coherent interconnect for multi-socket applications (up to 256 sockets)
- Specialized variants with FUs for database acceleration, security acceleration
- The cores can be a combination of C or I class, single thread performance driving the core choice.
- Interconnect TBD
- SoC configuration aimed at highly parallel enterprise, HPC and analytics workloads.
- 512 bit SIMD
- Optional L4 caches and an optimized memory hierarchy are responsible to achieve a high memory bandwidth.
- 64-bit in-order, multi-threaded, HPC variant with 32-100 cores
- The goal is 3-5 + Tflops (DP, sustained)
- A variant of the C-Class that explores tag based ISAs for object level security.
- Coarse grain tags will be used to deliver micro-VM like functionality and to mitigate software attacks like buffer-overflow.
- Single address space support, decoupling of protection from memory management.
- F-Class processors are fault-tolerant versions of the base processors.
- Features of F-Class includes temporal redundancy modules to detect permanent faults, redundant compute blocks, fault localization circuits, lock-step core configurations, ECC for critical memory blocks and redundant bus fabrics.
- These are also known as the key components of our ASIL-D solutions and autonomous vehicle compute blocks.
There are several advantages of using open-source software such as lower total cost of ownership, better access to innovation, extensive customization opportunities, fewer bugs, and so on.
While Shakti has so many advantages and has been built keeping in mind the key components required for enterprises, it will definitely provide “Shakti” to India’s electronic manufacturing ambitions.